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DS28CZ04: 4Kb I2C/SMBus EEPROM with Nonvolatile PIO
The common characteristic in both normal read cases is a starting address anywhere in the memory excluding
any address used for PIO access . The read pointer increments after every byte read. This way a series of read
accesses reveals memory data of consecutive addresses, without any duplications or gaps. When reading from
reserved areas the master receives FFh bytes. When the end of the upper half of the memory is reached (device
address A2h, address FFh) the read pointer wraps around to the start of the lower half of the memory (device
address A0h, address 00h). When the end of the lower half of the memory is reached, the read pointer continues at
the start of the upper half of the memory. To change the read address, the master has to address the DS28CZ04 in
write access mode and specify a new memory address.
The common characteristic in both PIO direct cases is a starting address within the address range used for PIO
access . In PIO Multi-Address Mode, there are four such addresses (7Ch to 7Fh); each PIO occupies its own
address. After a byte is sent to the master, the read pointer increments to the next PIO and eventually wraps
around to 7Ch. In PIO Single-Address Mode, there is exactly one address (7Ch) that is shared by all PIOs.
Consequently, the master can continue reading, but the read pointer stays at 7Ch.
When reading from a PIO, as shown in Figure 10, the sampling takes place on the falling SCL edge of the 2 nd -last
bit before the acknowledge bit. With PIO direct mode, the first sample is taken 3 SCL cycles earlier, i. e., during the
transmission of the A3 bit of the slave address. To be correctly assessed, the PIO state must not changed during
the t PS and t PH interval. In PIO Single-Address mode all PIOs are sampled simultaneously; in this mode with PIO
direct access the fastest sample rate for a PIO is f SCL /9. In PIO Multi-Address Mode each PIO is sampled individu-
ally; in this mode with PIO direct access the fastest sample rate for a PIO is f SCL /36. Transfer of data can be
stopped at any moment by a STOP condition. When this occurs, data from the last sampling instance is lost.
Figure 10. PIO Read Access Timing
Normal Read
Sampling
t PS
Sampling
t PH
Sampling
PIO
DATA1
DATA2
DATA3
DATA4
DATA5
SCL
SDA
MSB
(7Bh) data
LSB A MSB
DATA2
LSB A MSB
DATA3
LSB A MSB
DATA4
LSB A
PIO Direct
Sampling
t PS
Sampling
t PH
Sampling
PIO
DATA1
DATA2
DATA3
DATA4
DATA5
SCL
SDA
S A6 A5 A4 A3 A2 A1 P0 1
A MSB
DATA1
LSB A MSB
DATA3
LSB A MSB
DATA4
LSB A
With revision A1 devices, the sampling always takes place on the falling SCL edge of the last bit before the
acknowledge bit. The sampled data, however, is reported to the master one byte late, as shown in Figure 10A. The
first sample of PIO data that the master receives in PIO direct access should be discarded since its timing relative
to the transmission of the slave address is undefined. Any application firmware developed for revision A1 devices is
fully compatible to newer devices.
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